A semiconductor arrangement is described in European Patent No. 99 897, where into a substrate that is weakly doped with a first conductivity type is introduced a region of a second conductivity type, which, together with the substrate, forms a p-n junction. To influence the breakdown voltage between the introduced region and the substrate, a cover electrode, which is separated from the substrate by a thin oxide layer, is applied to the surface. The breakdown voltage of the p-n junction is regulated by adjusting the potential of this cover electrode by means of a voltage divider.
Likewise disclosed by European Patent No. 179 099 is a semiconductor arrangement of this kind, where the voltage divider is formed by variably doped integrated resistors. This achieves a certain compensation of the temperature dependency of the breakdown voltage. In this context, additional process steps are required because of the variably doped divider resistors. Furthermore, resistors of this kind require a comparatively large chip surface.